Successful tape-out using 5nm to 180nm TSMC, GF and other processes.
Taped out AI, CPU, and Networking processors up to 10Ghz speed.
RTL2GDSII implementation for both hierarchical chip and block level.
Met stringent PPA (power, performance, area requirement), on time, within budget.
Developed and automated floor planning, placement, routing, verification, and sign off flows and methodologies for Synopsys and Cadence tools up to latest nodes.
Process Technology: Up to 5 nm process technologies.
Foundries Used: TSMC, GF, Samsung, and other leading foundries.
EDA Vendor Tools: Synopsys, Cadence, Mentor Graphics, Ansys.
Key PnR Capabilities:
Flat, virtually flat, Hierarchical, and Chip-assembly flow
Floor planning, Placement Clock insertion, and Routing
Low power (UPF development) Design
Complex clocking scheme: clock mesh, multisource
Many clock domains (up to 5Ghz clock speed)
Advanced STA (MMMC, AOCV, POCV)
Multi-voltage design
Physical verification with IR/EM
Power Verification
Chip and block level Sign-off
ESD and Reliability analysis
Recent Accomplishment:
PNR with DFT verification of a highly complex Artificial Intelligence (AI) processor core at 6 Ghz using 7 nm process technology. Massive number of cores in a single chip.
Implementation of a Complex image processing, and networking processor chips.
