Our Custom Layout Design team has extensive expertise in advanced semiconductor technologies and EDA tools, with a proven track record of over 500 successful tape-outs across process nodes from 180nm to 2nm. We have worked with leading foundries such as TSMC, GlobalFoundries, Intel, Samsung, TowerJazz, UMC, and SMIC.
We specialize in high-quality full-custom layouts for biomedical, power management, LED driver, imaging chips, high-performance arrays, memory, SerDes, RF/mmWave, analog circuits, ADCs, DACs, regulators, PLLs, transmitters, receivers, DDR, and PHY interfaces. Guided by stringent performance and reliability standards, our work ensures precision and quality. Additionally, we excel in leaf cell layout, library development, and physical design verification.
Our engineers excel in end-to-end design, from Netlist to GDSII, across various nodes, with expertise in circuit matching, shielding, high-speed signal integrity, and ESD protection. With proficiency in tools like Cadence, Synopsys, Siemens, and Ansys, we ensure optimal performance, reliability, and compliance through rigorous verification and PERC validation. Our focus on process-driven solutions, high tapeout success, and biomedical IC innovations solidify our commitment to engineering excellence.
We deliver high-quality, production-ready layouts, excelling in device scaling and managing design rule complexities. With experience across various process nodes and EDA tools, we are known for reliability and precision, ensuring optimized performance and manufacturability for clients' success in the competitive market.
Expertise Section:
Title: Core Competencies
Analog and mixed-signal layout design
Digital layout design
RF layout design
Full Chip
IP design
ADC and DAC
PLL
Band gap reference
I/O circuits
SerDes
Standard cell library development
Memory Design
Post-layout analysis
Custom Layout Expertise:
Full Chip Design:
Expertise in Biomedical Chips, Power Management Chips, LED Drivers, and Imaging Chips.
Designed and validated 10+ test chips across multiple process nodes for cutting-edge technology development.
Successfully developed and taped out 5+ full-custom biomedical chips tailored to specialized medical and research applications..
Developed 10+ full-chip power management implementations.
SerDes IP Design:
Expertise in SerDes IP design from 180nm to 3nm nodes. Completed 30+ SERDES layouts.
Emphasis on tight matching for optimal performance.
Special attention to key components such as CTLE, driver, bandgap, and SSCG PLL.
ensuring high-speed data communication and signal integrity.
Memory layout design:
Successfully taped out 250+ memory layout projects.
Proven capability in designing Level 1, Level 2, and Level 3 cache architectures across a wide range of process nodes (2-28 nm), with a focus on high-density configurations, multi-bank designs, and high-performance clock speeds.
Extensive experience in developing Level 1 & 2 cache tags and Level 2 test chips, ensuring optimal performance and reliability in advanced cache systems.
IP design:
Digital Frequency Synthesizer:6+ Cells, Nodes: 2-7 nm, Up to 5 phases, Up to 4 GHz clock speed
Clock Control: 4+ Cells, Nodes: 2-14 nm, Up to 4 GHz clock speed
Custom Power Grid (PG): 5+ Cells, Nodes: 2-7 nm, Thermal, EM, and IR verified
Standard Cells and Flops: 5000+ Cells, Nodes: 3-28 nm, Timing, DRC, EDRC, Setup/hold verified.
PLL (LCPLL, HSPLL, SSCG):
Extensive experience with PLL circuits across various process nodes
Extensive experience in Inductor-Capacitor Phase-Locked Loop, High-Speed Phase-Locked Loop, Spread Spectrum Clock Generator design.
BGR (Bandgap Reference) Design:
Experienced in bandgap reference (BGR) circuit design
Skilled in precise resistor matching for improved design accuracy
Expertise in power planning to ensure optimal performance and efficiency
Proven ability to meet stringent voltage stability and temperature independence requirements
Digital Layout Design:
Delivered 6+ high-precision digital frequency synthesizer designs for advanced applications.
Executed 4+ clock control design projects, ensuring optimal timing and synchronization.
Completed 5000+ Standard Cells, cross advanced process nodes including 3-28 nm and Timing, DRC, EDRC, Setup/hold verified.
Successfully taped out 250+ memory layout projects, including L1, L2, and L3 data & tag architectures from scratch.
