ARCHITECTURE AND RTL DESIGN

ARCHITECTURE AND RTL DESIGN

Experienced in developing Soft IP

SPI, UART, GPIO’s, etc.

ARM M3 based SoC

Competencies

U-arch development from specs.

Robust RTL coding guideline.

RTL coding in Verilog and System Verilog.

RAL(IPXACT) to minimize u-arch to RTL errors (e.g. user registers).

Lint checking(spyglass) to enforce design guidelines.

Debug ability with GUI tools, and waveform, UVM testbench.

Code coverage analysis, Verification, Synthesis, Timing Analysis.

Robust design methodology that produces functional,

synthesizable, RTL that meets Timing, and DFT ready.

Flop based RTL design (no latches), single clock domain, DFT ready.

Clock-gating for power efficiency.

EDA Vendor Tools: Cadence, Synopsys.

 

ARCHITECTURE AND RTL DESIGN