DESIGN FOR TEST (DFT)

DESIGN FOR TEST (DFT)

The DFT team is dedicated to achieving testability to detect manufacturing defects in the designs. As DFT is a vital and often challenging step, our team simplifies and optimizes it, ultimately reducing costs and accelerating time-to-market.

With expertise in scan insertion, Automatic Test Pattern Generation (ATPG), Boundary Scan/JTAG, and coverage analysis, we provide comprehensive DFT solutions at both the IP and SoC levels. Our team focuses on maximizing test coverage, reducing test time, and improving yield, ensuring that your final product meets the highest quality standards.

By adopting advanced DFT methodologies and the latest industry tools, Ulkasemi’s team integrates efficient and effective test strategies throughout the design flow. Our goal is to deliver reliable, cost-effective test solutions that enhance the overall success and reliability of your SoC design.

DESIGN FOR TEST (DFT)

CAPABILITIES SUMMARY

Development of DFT Architecture & Specification

Flow development and implementation based on DFT architecture in block and SoC level

DFT Scannability check with Spyglass

Scan Insertion with or without Compression

Implementation of DFT IPs such as On-Chip Clock Controller, SSN (Streaming Scan Network), etc.

mplementation of MBIST, LBIST, Boundary scan & JTAG/IJTAG

Insertion of DFT features like Test Point, Wrapper, etc. for coverage improvement

LINT and LEC on DFT inserted design

Test vector generation using ATPG

Coverage analysis and improvement

Low-power ATPG and low-power compression

Gate-level simulation and debugging with no-timing and timing

Diagnosis for silicon failure

Exposures in industry-standard EDA tools such as Synopsys, Mentor Graphics