ULKASEMI supports turnkey SOC design from RTL to GDSII.

• DFT verification for successful silicon tape-outs
• Deliver designs that meet very stringent requirements for area, power, and performance.
• Expert in handling multi-voltage, MCMM, complex clocking schemes, and flat, virtually flat, hierarchical, chip-assembly flow.
• Tools/Methodology: Developed physical design flows and methodologies from 180 nm to 7 nm technologies using Synopsys, Cadence, and Mentor Graphics tools
• Supports TSMC and all leading foundries

Our foundry support and design enablement team provides the following services from 28 nm to latest node:

• Process development and optimization
• Standard cell library development and characterization
• IPTEST, PPA, MHC
• Analog and complex IP development
• Tool development and process automation

We offer extensive digital verification services including:

• Chip, block and IP-level verification
• Turnkey verification using modular and reusable design environment
• Faster turnaround time and high quality, excellent coverage
• Uses both System Verilog verification and Assertion base coverage
• Randomize and directed tests
• UVM VIP development, ABV, and metric-driven verification methodology
• Tools/Methodology:  Cadence, Synopsys,  and Mentor Graphics verification tools

ULKASEMI provides Analog/AMS verification services: