Functional Verification is often the most resource intensive and costly part of the SoC hardware design process. Ulkasemi’s engineering team can starting verification early in the design cycle by streamlining testbench development, facilitating faster turnaround times and high quality, reliable designs.

Ulkasemi’s expertise covers a comprehensive range of skills including test plan creation, testbench development and design debug at both IP block and SoC level. We are able to bring the latest testbench verification methodologies such as UVM VIP development, ABV and metric driven verification.

• Feature extraction from Specification.
• Develop test plan which includes stimulus generation plan, functionality checking and coverage modeling.
• Review the test plan with Design team.
• Develop testbench environment and other components for verifying each block in design.
• Create necessary test cases to ensure desired functionality of each block.
• Run Regression tests at block level and report bugs in RTL.
• Create directed and randomized test cases to check corner cases in design.
• Integrate all blocks and reuse block level verification components to verify the design at system level.
• Run tests at system level to ensure correct block integration. Proceed with system level regression testing to verify system functionality and generate coverage reports.