Upcoming Event


Workshop Venue: East West University

Workshop Type: Day Long Workshop

Workshop Dates: 5th, 12th, 19th and 26th October

Workshop will be conducted by 4 departments
  • Front-End Verification
  • Circuit Design
  • IC Layout Design
  • IC Placing and Routing
Agenda that will be covered by all 4 departments:
  1. Front-End Verification: A Brief Introduction to ASIC Front-End Verification
    Front End Verification is the method of checking the functional equivalency between the RTL and the specification using a complex program called “testbench”. In our daily life we utilize a lot of electronics that utilize various complex chips to perform their intended operation. Application Specific Integrated Circuit (ASIC) is everywhere around us, from simple elevator control to complex spaceship control. All these ASIC chips need to be bug free. Job of functional verification engineer is to ensure that the design is bug free and it meets the specification by rigorously testing the design for all possible combination of control settings and input stimulus. However, doing this by hand is very tedious so the verification engineers write a complex program known as testbench using a hardware verification language called SystemVerilog.In this workshop we will walk you through the entire process of ASIC design and verification so that by the end of the session you will have the basic understanding of how an IC is made and verified.
      What you will learn in this workshop
    • ASIC design flow
    • A brief introduction to SystemVerilog as Hardware Verification language (HVL)
    • Front-End Verification flow
    • Introduction on class based testbench
    • Hands on experience about developing a class based testbench to verify a RTL design using SystemVerilog.
    • How to run the simulation using Cadence Incisive environment (IUS)
    • Functional and Code coverage analysis

  2. Circuit Design: A Brief Introduction to Circuit Design
      What you will learn in this workshop
    • Circuit Design Fundamentals
    • Circuit Design type, applications etc.
    • Analog/Custom IC Design Flow
    • Basic Circuit Design Topology
    • Circuit Simulation (Pre-Layout)
    • Parasitic & Circuit Simulation (Post-Layout)
    • Simulation Automation
    • Basic Device operation
    • Design of an Example Circuit.
    • Simulation and measurements of the Example Circuit.
    • Future Scopes

  3. IC Layout Design: A Brief Introduction to IC Layout Design
      What you will learn in this workshop
    • Basics of layout.
    • Analogue and Digital layout techniques.
    • Custom and Standard layout design
    • Solving LVS, DRC and ERC issues.

  4. IC Placing and Routing: A Brief Introduction to IC Placing & Routing
    Physical design process is often referred as PnR (Place and Route) / APR (Automatic Place & Route). The design-cycle of VLSI-chips consists of different consecutive steps from high-level synthesis (functional design) to production. The physical design is the process of transforming a circuit description into the physical layout. Main steps in physical design are placement of all logical cells, clock tree synthesis & routing. During this process of physical design timing, power, design & technology constraints have to be met. Furthermore, design is often optimized w.r.t area, power and performance
      What you will learn in this workshop
    • ASIC Design Flow
    • Place and Route Flow
    • Logic synthesis (RTL to Gate level on genus)
    • Floor Planning
    • Basics of Clock Tree Synthesis (CTS)
    • Routing
    • Signoff Flow
    • Challenging Designs Done by Ulkasemi