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Work with the RTL design team on understanding design in context of physical design timing closure including development of timing constraints required for implementation.
Work with the DFT team on understanding DFT design in regards to physical design timing closure.
Lead core and Top level timing closure activities.
Develop new scripts/flows to improve the timing closure process.
Complete Physical Implementation of cores i.e. graphics, video, multimedia, processor, DDR.
Low-power implementation methods.
Core and Top level Floorplanning, placement, CTS, P&R, PV, and Signal Integrity Analysis.
Develop high speed customized logic cells.
Simple to complex Standard cell layout design
Floor planning, architecture definition and physical layout implementation against the schematic design of Standard cells
Validating the layout for DRC (design rule), LVS (Layout versus schematic), DFM (design for manufacturability) ERC (electrical rule) ORC (optical rule) EM /IR (electro migration and IR drop) checks
Good understanding of usage of standard cells
Any scripting language proficiency is also desirable
Functional Verification of ASIC designs.
Test planning and Testbench development using
Hardware Verification Languages (Verilog,SystemVerilog, Ve rilog-AMS).
RTL Simulation, regression testing, debugging and coverage reporting.
Exoosure to CAD tools such as Cadence lUS, Active HDL, Xilinx lSE, Precision, etc.
Programming Languages such as C, C++ (Scripting languages bash/Perl would be a plus).
Keen interest, passion and self-motivation for working in the semiconductor field.
Good communication skills in English.